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LTC3417 Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator
FEATURES

DESCRIPTIO
High Efficiency: Up to 95% 1.4A/800mA Guaranteed Minimum Output Current No Schottky Diodes Required Programmable Frequency Operation: 1.5MHz or Adjustable From 0.6MHz to 4MHz Low RDS(ON) Internal Switches Short-Circuit Protected VIN: 2.25V to 5.5V Current Mode Operation for Excellent Line and Load Transient Response 125A Quiescent Current in Sleep Mode Ultralow Shutdown Current: IQ < 1A Low Dropout Operation: 100% Duty Cycle Power Good Output Phase Pin Selects 2nd Channel Phase Relationship with Respect to 1st Channel Internal Soft-Start with Individual Run Pin Control Available in Small Thermally Enhanced (5mm x 3mm) DFN and 20-Lead TSSOP Packages
The LTC(R)3417 is a dual constant frequency, synchronous step-down DC/DC converter. Intended for medium power applications, it operates from a 2.25V to 5.5V input voltage range and has a constant programmable switching frequency, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. Each output voltage is adjustable from 0.8V to 5V. Internal synchronous low RDS(ON) power switches provide high efficiency without the need for external Schottky diodes. A user selectable mode input allows the user to trade off ripple voltage for light load efficiency. Burst Mode(R) operation provides high efficiency at light loads, while Pulse Skip mode provides low ripple noise at light loads. A phase mode pin allows the second channel to operate in-phase or 180 out-of-phase with respect to channel 1. Out-ofphase operation produces lower RMS current on VIN and thus lower RMS derating on the input capacitor. To further maximize battery life, the P-channel MOSFETs are turned on continuously in dropout (100% duty cycle) and both channels draw a total quiescent current of only 100A. In shutdown, the device draws <1A.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6144194
APPLICATIO S

PDAs/Palmtop PCs Digital Cameras Cellular Phones PC Cards Wireless and DSL Modems
TYPICAL APPLICATIO
VIN 2.5V TO 5.5V 10F VOUT1 1.8V 1.4A 1.5H 22pF VIN 511k VFB1 22F 412k ITH1 5.9k 2200pF FREQ SW1 RUN1
OUT2 Efficiency (Burst Mode Operation)
100 REFER TO FIGURE 4 10 95
VIN
EFFICIENCY (%)
2.2H SW2 RUN2 LTC3417 VFB2 VIN 866k 412k ITH2 GND 2.87k 6800pF
3417 TA01
22pF
VOUT2 2.5V 800mA
90 0.1 85 0.01 80 75 70 0.001 POWER LOSS VIN = 3.6V VOUT = 2.5V FREQ = 1MHz 0.01 0.1 LOAD CURRENT (A) 1
3417 TA01a
10F
U
1 EFFICIENCY
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POWER LOSS (W)
0.001
0.0001
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1
LTC3417
ABSOLUTE
AXI U
RATI GS (Note 1)
Operating Ambient Temperature Range (Note 2) .................................................. - 40C to 85C Junction Temperature (Notes 7, 8) ...................... 125C Storage Temperature Range DFN Package ................................... - 65C to 125C TSSOP Package ............................... - 65C to 150C
VIN1, VIN2 Voltages ..................................... - 0.3V to 6V MODE, SW1, SW2, RUN1, RUN2, VFB1, VFB2, PHASE, FREQ, ITH1, ITH2 Voltages ............. - 0.3V to (VIN1/VIN2 + 0.3V) VIN1 - VIN2, VIN2 - VIN1 ......................................... 0.3V PGOOD Voltage .......................................... - 0.3V to 6V
PACKAGE/ORDER I FOR ATIO
TOP VIEW RUN1 VIN1 ITH1 VFB1 VFB2 ITH2 RUN2 VIN2 1 2 3 4 5 6 7 8 17 16 PGND1 15 SW1 14 PHASE 13 GNDA 12 FREQ 11 PGOOD 10 SW2 9 MODE
ORDER PART NUMBER LTC3417EDHC
DHC PART MARKING 3417
DHC PACKAGE 16-LEAD (3mm x 5mm) PLASTIC DFN
TJMAX = 125C, JA = 43C/ W EXPOSED PAD (PIN 17) IS PGND2/GNDD MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise specified. (Note 2)
SYMBOL VIN1, VIN2 IFB1, IFB2 VFB1, VFB2 VLINEREG VLOADREG gm(EA) PARAMETER Operating Voltage Range Feedback Pin Input Current Feedback Voltage Reference Voltage Line Regulation. %/V is the Percentage Change in VOUT with a Change in VIN Output Voltage Load Regulation Error Amplifier Transconductance CONDITIONS VIN1 = VIN2 (Note 3) (Note 3) VIN = 2.25V to 5V (Note 3) ITH1, ITH2 = 0.36V (Note 3) ITH1, ITH2 = 0.84V (Note 3) ITH1, ITH2(PINLOAD) = 5A (Note 3) 0.784 0.8 0.04 0.02 -0.02 1400 MIN 2.25 TYP MAX 5.5 0.1 0.816 0.2 0.2 -0.2 UNITS V A V %/V % % S
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TOP VIEW GNDD RUN1 VIN1 ITH1 VFB1 VFB2 ITH2 RUN2 VIN2 1 2 3 4 5 6 7 8 9 21 20 GNDD 19 PGND1 18 SW1 17 PHASE 16 GNDA 15 FREQ 14 PGOOD 13 SW2 12 MODE 11 PGND2
ORDER PART NUMBER LTC3417EFE
PGND2 10
FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 38C/ W EXPOSED PAD (PIN 21) IS PGND2/GNDD MUST BE SOLDERED TO PCB
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LTC3417
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise specified. (Note 2)
SYMBOL IS PARAMETER Input DC Supply Current (Note 4) Active Mode Half Active Mode (VRUN2 = 0V, 1.4A Only) Both Channels in Sleep Mode Shutdown fOSC Oscillator Frequency CONDITIONS VFB1 = VFB2 = 0.75V, VMODE = VIN, VRUN1 = VRUN2 = VIN VFB1 = 0.75V, VMODE = VIN, VRUN1 = VIN VFB1 = VFB2 = 1V, VMODE = VIN, VRUN1 = VRUN2 = VIN VRUN1 = VRUN2 = 0V VFREQ = VIN VFREQ: RT = 143k VFREQ: Resistor (Note 6) 1.2 0.85 1.8 1 VIN1 = 3.6V (Note 5) VIN1 = 3.6V (Note 5) VIN2 = 3.6V (Note 5) VIN2 = 3.6V (Note 5) VIN1 = 6V, VITH1 = 0V, VRUN1 = 0V VIN2 = 6V, VITH2 = 0V, VRUN2 = 0V VIN1, VIN2 Ramping Down VIN1, VIN2 Ramping Up VFB1 or VFB2 Ramping Up, VMODE = 0V VFB1 or VFB2 Ramping Down, VMODE = 0V 1.9 1.95 MIN TYP 400 260 260 125 0.1 1.5 1 2.25 1.2 0.088 0.084 0.16 0.15 0.01 0.01 2.07 2.12 -6 -6 160 0.3 VIN -0.5 0.5 VIN = 6V, PVIN = 3V 0.01 1 0.5 VIN -0.5 VIN -0.5 0.85 300 1.5 1 1 2.2 2.25 MAX 600 400 400 250 1 1.8 1.25 4 UNITS A A A A A MHz MHz MHz A A A A V V % % V V V A V V V
Half Active Mode (VRUN1 = 0V, 800mA Only) VFB2 = 0.75V, VMODE = VIN, VRUN2 = VIN
ILIM1 ILIM2 RDS(ON)1 RDS(ON)2 ISW1(LKG) ISW2(LKG) VUVLO TPGOOD
Peak Switch Current Limit on SW1 (1.4A) Peak Switch Current Limit on SW2 (800mA) SW1 Top Switch On-Resistance (1.4A) SW1 Bottom Switch On-Resistance SW2 Top Switch On-Resistance (800mA) SW2 Bottom Switch On-Resistance Switch Leakage Current SW1 (1.4A) Switch Leakage Current SW2 (800mA) Undervoltage Lockout Threshold Threshold for Power Good. Percentage Deviation from VFB Steady State (Typically 0.8V) Power Good Pull-Down On-Resistance RUN1, RUN2 Threshold PHASE Threshold High-CMOS Levels PHASE Threshold Low-CMOS Levels
RPGOOD VRUN1, VRUN2 VPHASE
IRUN1, IRUN2, RUN1, RUN2, PHASE and MODE IPHASE, IMODE Leakage Current VTLMODE VTHMODE VTHFREQ MODE Threshold Voltage Low MODE Threshold Voltage High FREQ Threshold Voltage High
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3417 is guaranteed to meet specified performance from 0C to 70C. Specifications over the -40C to 85C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3417 is tested in feedback loop which servos VFB1 to the midpoint for the error amplifier (VITH1 = 0.6V) and VFB2 to the midpoint for the error amplifier (VITH2 = 0.6V). Note 4: Total supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: Switch on-resistance is guaranteed by design and test correlation on the DHC package and by final test correlation on the FE package.
Note 6: Variable frequency operation with resistor is guaranteed by design but not production tested and is subject to duty cycle limitations. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: LTC3417EDHC: TJ = TA + (PD * 43C/W) LTC3417EFE: TJ = TA + (PD * 38C/W)
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LTC3417 TYPICAL PERFOR A CE CHARACTERISTICS
OUT1 Burst Mode Operation OUT1 Pulse Skipping Mode Operation OUT1 Forced Continuous Mode Operation
VOUT 20mV/DIV
IL 250mA/DIV
VIN = 3.6V 2s/DIV VOUT = 1.8V ILOAD = 100mA REFER TO FIGURE 4
OUT2 Burst Mode Operation
VOUT 20mV/DIV
IL 250mA/DIV
VIN = 3.6V 2s/DIV VOUT = 2.5V ILOAD = 60mA REFER TO FIGURE 4
OUT1 Efficiency vs Load Current
100 VIN = 2.5V 95 VOUT = 1.8V 90 100
EFFICIENCY (%)
EFFICIENCY (%)
85 80 75 70 65 60 0.001 0.01 0.1 Burst Mode OPERATION PULSE SKIP FORCED CONTINUOUS REFER TO FIGURE 4 1 10 LOAD CURRENT (A)
3417 G07
85 80 75 70 65 60 0.001 0.01 Burst Mode OPERATION PULSE SKIP FORCED CONTINUOUS REFER TO FIGURE 4 0.1 1 LOAD CURRENT (A)
3417 G08
EFFICIENCY (%)
4
UW
VOUT 20mV/DIV
VOUT 20mV/DIV
IL 250mA/DIV
IL 250mA/DIV
3417 G01
VIN = 3.6V 2s/DIV VOUT = 1.8V ILOAD = 100mA REFER TO FIGURE 4
3417 G02
VIN = 3.6V 2s/DIV VOUT = 1.8V ILOAD = 100mA REFER TO FIGURE 4
3417 G03
OUT2 Pulse Skipping Mode Operation
OUT2 Forced Continuous Mode Operation
VOUT 20mV/DIV
VOUT 20mV/DIV
IL 250mA/DIV
IL 250mA/DIV
3417 G04
VIN = 3.6V 2s/DIV VOUT = 2.5V ILOAD = 60mA REFER TO FIGURE 4
3417 G05
VIN = 3.6V 2s/DIV VOUT = 2.5V ILOAD = 60mA REFER TO FIGURE 4
3417 G06
OUT2 Efficiency vs Load Current
VIN = 3.6V 95 VOUT = 2.5V 90 90 100 95
OUT1 Efficiency vs VIN (Burst Mode Operation)
VOUT = 1.8V ILOAD = 460mA
ILOAD = 1.4A 85 80 75 70 2 2.5 3 3.5 REFER TO FIGURE 4 4 4.5 5 5.5 VIN (V)
3417 G09
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LTC3417
TYPICAL PERFOR A CE CHARACTERISTICS
OUT2 Efficiency vs VIN (Pulse Skipping Mode)
100
ILOAD = 250mA
95
EFFICIENCY (%)
90
85 80 75 70
ILOAD = 800mA
VOUT = 2.5V REFER TO FIGURE 4
2
2.5
3
3.5
4
4.5
VIN (V)
3417 G10
Efficiency vs Frequency OUT1
94 92 90 88 86 84 82 0 1 2 3 4
5
TA = 27C VIN = 3.6V VOUT = 1.8V IOUT = 300mA
EFFICIENCY (%)
EFFICIENCY (%)
RDS(ON) ()
FREQUENCY (MHz)
3417 G13
RDS(ON) vs VIN OUT2
0.20 0.19 0.18
P-CHANNEL SWITCH TA = 27C
FREQUENCY VARIATION (%)
2 0
-2
FREQ = 143k TO GROUND
FREQUENCY VARIATION (%)
RDS(ON) ()
0.17 0.16 0.15
N-CHANNEL SWITCH
0.14
2
2.5
3
3.5
4
4.5
VIN (V)
3417 G16
UW
5
5
Load Step OUT1
Load Step OUT2
VOUT1 100mV/DIV
VOUT2 100mV/DIV
IOUT1 500mA/DIV
IOUT2 500mA/DIV
5.5
VIN = 3.6V 100s/DIV VOUT = 1.8V ILOAD = 0.25A to 1.4A REFER TO FIGURE 4
3417 G11
VIN = 3.6V 100s/DIV VOUT = 2.5V ILOAD = 0.25A to 0.8A REFER TO FIGURE 4
3417 G12
Efficiency vs Frequency OUT2
90 85 80
0.095 0.105
RDS(ON) vs VIN OUT1
TA = 27C
0.100
P-CHANNEL SWITCH
75 70 65
TA = 27C VIN = 3.6V VOUT = 2.5V IOUT = 100mA
0.090
0.085
N-CHANNEL SWITCH
60 0
1 2
3
4
0.080 2 2.5 3 3.5 4 4.5 5 5.5 VIN (V)
FREQUENCY (MHz)
3417 G14
3417 G15
Frequency vs VIN
6
15 10 5
0
Frequency vs Temperature
4
FREQ = VIN
FREQ = 143k TO GROUND
-4
FREQ = VIN
-5 -10
-6 -8
5.5
-10
2
2.5
3
3.5
4
4.5
5
5.5
-15 -50 -25
0
25
50
75
100
125
VIN (V)
3417 G17
TEMPERATURE (C)
3417 G18
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LTC3417
PI FU CTIO S (DFN/TSSOP)
RUN1 (Pin 1/Pin 2): Enable for 1.4A Regulator. When at Logic 1, 1.4A regulator is running. When at 0V, 1.4A regulator is off. When both RUN1 and RUN2 are at 0V, the part is in shutdown. VIN1 (Pin 2/Pin 3): Supply Pin for P-Channel Switch of 1.4A Regulator. ITH1 (Pin 3/Pin 4): Error Amplifier Compensation Point for 1.4A Regulator. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.5V. VFB1 (Pin 4/Pin 5): Receives the feedback voltage from external resistive divider across the 1.4A regulator output. Nominal voltage for this pin is 0.8V. VFB2 (Pin 5/Pin 6): Receives the feedback voltage from external resistive divider across the 800mA regulator output. Nominal voltage for this pin is 0.8V. ITH2 (Pin 6/Pin 7): Error Amplifier Compensation Point for 800mA regulator. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.5V. RUN2 (Pin 7/Pin 8): Enable for 800mA Regulator. When at Logic 1, 800mA regulator is running. When at 0V, 800mA regulator is off. When both RUN1 and RUN2 are at 0V, the part is in shutdown. VIN2 (Pin 8/Pin 9): Supply Pin for P-Channel Switch of 800mA Regulator and Supply for Analog Circuitry. MODE (Pin 9/Pin 12): Mode Selection Pin. This pin controls the operation of the device. When the voltage on the MODE pin is >(VIN - 0.5V), Burst Mode operation is selected. When the voltage on the MODE pin is <0.5V, pulse skipping mode is selected. When the MODE pin is held at VIN/2, forced continuous mode is selected. SW2 (Pin 10/Pin 13): Switch Node Connection to the Inductor for the 800mA Regulator. This pin swings from VIN2 to PGND2. PGOOD (Pin 11/Pin 14): Power Good Pin. This common drain-logic output is pulled to GND when the output voltage of either regulator is - 6% of regulation. If either RUN1 or RUN2 is low (the respective regulator is in sleep mode and therefore the output voltage is low), then PGOOD reflects the regulation of the running regulator. FREQ (Pin 12/Pin 15): Frequency Set Pin. When FREQ is at VIN, internal oscillator runs at 1.5MHz. When a resistor is connected from this pin to ground, the internal oscillator frequency can be varied from 0.6MHz to 4MHz. GNDA (Pin 13/Pin 16): Analog Ground Pin for Internal Analog Circuitry. PHASE (Pin 14/Pin 17): Selects 800mA regulator switching phase with respect to 1.4A regulator switching. Set to VIN, the 1.4A regulator and the 800mA regulator are in phase. When PHASE is at 0V, the 1.4A regulator and the 800mA regulator are switching 180 degrees out-of-phase. SW1 (Pin 15/Pin 18): Switch Node Connection to the Inductor for the 1.4A Regulator. This pin swings from VIN1 to PGND1. PGND1 (Pin 16/Pin 19): Ground for SW1 N-Channel Driver. PGND2, GNDD (Pins 1,10,11,20): TSSOP Package Only. Ground for SW2 N-channel driver and digital ground for circuit. Exposed Pad (Pin 17/Pin 21): PGND2, GNDD. Ground for SW2 N-channel driver and digital ground for circuit. The Exposed Pad must be soldered to PCB ground.
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LTC3417
FU CTIO AL DIAGRA
1.4A REGULATOR
+
VFB1
-
VB SLOPE COMPENSATION ANTI-SHOOTTHROUGH SW1
0.752V
+ -
+
LOGIC 0.848V
- - +
PGND1
RUN1
VOLTAGE REFERENCE
VIN2
RUN2 PHASE MODE OSCILLATOR FREQ
0.848V
LOGIC
ANTI-SHOOTTHROUGH SLOPE COMPENSATION
0.752V
- +
ITH2 ITH LIMIT
800mA REGULATOR
+
-
VFB2
VB
+
-
-
-
+
+
+
-
W
ITH1 ITH LIMIT VIN1
+
+
-
-
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+ -
+ -
PGOOD
PGND2
SW2
VIN2
3417 BD
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LTC3417
OPERATIO
The LTC3417 uses a constant frequency, current mode architecture. Both channels share the same clock frequency. The PHASE pin sets whether the channels are running in-phase or out of phase. The operating frequency is determined by connecting the FREQ pin to VIN for 1.5MHz operation or by connecting a resistor from FREQ to ground for a frequency from 0.6MHz to 4MHz. To suit a variety of applications, the MODE pin allows the user to trade off noise for efficiency. The output voltages are set by external dividers returned to the VFB1 and VFB2 pins. An error amplifier compares the divided output voltage with a reference voltage of 0.8V and adjusts the peak inductor current accordingly. Undervoltage comparators will pull the PGOOD output low when either output voltage is 6% below its targeted value. Main Control Loop For each regulator, during normal operation, the P-channel MOSFET power switch is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom N-channel MOSFET switch into the load until the next clock cycle. The peak inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier. This amplifier compares the VFB pin to the 0.8V reference. When the load current increases the VFB voltage decreases slightly below the reference. This decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The main control loop is shut down by pulling the RUN pin to ground. A digital soft-start is enabled after shutdown, which will slowly ramp the peak inductor current up over 1024 clock cycles.
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Low Current Operation Three modes are available to control the operation of the LTC3417 at low currents. Each of the three modes automatically switch from continuous operation to the selected mode when the load current is low. To optimize efficiency, Burst Mode operation can be selected. When the load is relatively light, the LTC3417 automatically switches into Burst Mode operation in which the PMOS switches operate intermittently based on load demand. By running cycles periodically, the switching losses, which are dominated by the gate charge losses of the power MOSFETs, are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. The hysteresis voltage comparator trips when ITH is below 0.24V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH exceeds 0.31V, turning on the switch and the main control loop which starts another cycle. For lower output voltage ripple at low currents, pulse skipping mode can be used. In this mode, the LTC3417 continues to switch at constant frequency down to very low currents, where it will begin skipping pulses used to control the power MOSFETs. Finally, in forced continuous mode, the inductor current is constantly cycled creating a fixed output voltage ripple at all output current levels. This feature is desirable in telecommunications since the noise is a constant frequency and is thus easy to filter out. Another advantage of this mode is that the regulator is capable of both sourcing current into a load and sinking some current from the output. The mode selection for the LTC3417 is set using the MODE pin. The MODE pin sets the mode for both the 800mA and the 1.4A step-down DC/DC converters.
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LTC3417
OPERATIO
Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100%. In this dropout condition, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal Pchannel MOSFET and inductor.
APPLICATIO S I FOR ATIO
RT (k)
A general LTC3417 application circuit is shown in Figure 4. External component selection is driven by the load requirement, and begins with the selection of the inductors L1 and L2. Once L1 and L2 are chosen, CIN, COUT1 and COUT2 can be selected. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency, fO, of the LTC3417 is determined by pulling the FREQ pin to VIN for 1.5MHz operation or by connecting an external resistor from FREQ to ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation:
RT = 1 . 61* 1011 () - 16 . 586k fO
for 0.6MHz fO 4MHz. Alternatively, use Figure 1 to select the value for RT. The maximum operating frequency is also constrained by the minimum on-time and duty cycle. This can be calculated as:
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Low Supply Operation The LTC3417 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2.07V to prevent unstable operation.
160 140 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 FREQUENCY (MHz)
3417 F01
Figure 1. Frequency vs RT
V fO(MAX) 6.67 OUT (MHz) VIN(MAX)
The minimum frequency is limited by leakage and noise coupling due to the large resistance of RT. Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current, IL, decreases with higher inductance and increases with higher VIN or VOUT.
IL =
VOUT VOUT 1- fO * L VIN
Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple, greater core losses and lower output current capability.
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LTC3417
APPLICATIO S I FOR ATIO
A reasonable starting point for setting ripple current is IL = 0.35ILOAD(MAX), where ILOAD(MAX) is the maximum current output. The largest ripple, IL, occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation:
L=
VOUT VOUT 1- V fO * IL IN(MAX)
The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductor values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements of any
Table 1
MANUFACTURER L1 on OUT1 Toko Coilcraft Sumida Midcom L2 on OUT2 Toko Coilcraft Sumida Midcom A915AY-2R0M-D53LC DO1608C-222ML CDRH3D16/HP 2R2 CDRH2D18/HP 2R2 DUP-1813-2R2R 2.0 2.2 2.2 2.2 2.2 A920CY-1R5M-D62CB A918CY-1R5M-D62LCB DO1608C-152ML CDRH4D22/HP 1R5 CDRH2D18/HP 1R7 DUP-1813-1R4R 1.5 1.5 1.5 1.5 1.7 1.4 PART NUMBER VALUE (H)
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radiated field/EMI requirements than on what the LTC3417 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3417 applications. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter can be approximated by the sum of two square waves with duty cycles of approximately VOUT1/VIN and VOUT2/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. Some capacitors have a derating spec for maximum RMS current. If the capacitor being used has this requirement, it is necessary to calculate the maximum RMS current. The RMS current calculation is different if the part is used in "in phase" or "out of phase". For "in phase", there are two different equations: VOUT1 > VOUT2:
IRMS = 2 * I1 * I2 * D2(1 - D1) + I22 (D2 - D22 ) + I12 (D1 - D12 )
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VOUT2 > VOUT1:
IRMS = 2 * I1 * I2 * D1(1 - D2) + I22 (D2 - D22 ) + I12 (D1 - D12 )
where:
D1 =
VOUT1 V and D2 = OUT2 VIN VIN
DCR 0.014 0.018 0.06 0.031 0.035 0.033 0.027 0.07 0.047 0.035 0.047 DIMENSIONS L x W x H (mm) 6 x 6 x 2.5 6x6x2 6.6 x 4.5 x 2.9 5 x 5 x 2.4 3.2 x 3.2 x 2 4.3 x 4.8 x 3.5 5x5x3 6.6 x 4.5 x 2.9 4 x 4 x 1.8 3.2 x 3.2 x 2 4.3 x 4.8 x 3.5
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MAX DC CURRENT (A) 2.8 2.9 2.6 3.9 1.8 5.5 3.9 2.3 1.75 1.6 3.9
LTC3417
APPLICATIO S I FOR ATIO
When D1 = D2 then the equation simplifies to: IRMS = (I1 + I2 ) D(1- D) or
IRMS = (I1 + I2 ) VOUT ( VIN - VOUT ) VIN
where the maximum average output currents I1 and I2 equal the respective peak currents minus half the peak-topeak ripple currents: IL1 2 IL2 I2 = ILIM2 - 2 I1 = ILIM1 - These formula have a maximum at VIN = 2VOUT, where IRMS = (I1 + I2)/2. This simple worst case is commonly used to determine the highest IRMS. For "out of phase" operation, the ripple current can be lower than the "in phase" current. In the "out of phase" case, the maximum IRMS does not occur when VOUT1 = VOUT2. The maximum typically occurs when VOUT1 - VIN/2 = VOUT2 or when VOUT2 - VIN/2 = VOUT1. As a good rule of thumb, the amount of worst case ripple is about 75% of the worst case ripple in the "in phase" mode. Also note that when VOUT1 = VOUT2 = VIN/2 and I1 = I2, the ripple is zero. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1F to 1F ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution.
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Output Capacitor (COUT1 and COUT2) Selection The selection of COUT1 and COUT2 is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (VOUT) is determined by:
1 VOUT IL ESRCOUT + 8 * fO * COUT
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where fO = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage, since IL increases with input voltage. With IL = 0.35ILOAD(MAX), the output ripple will be less than 100mV at maximum VIN and fO = 1MHz with: ESRCOUT < 150m Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely cost-sensitive applications provided that consideration is
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APPLICATIO S I FOR ATIO
given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, high voltage and temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. In most cases, 0.1F to 1F of ceramic capacitors should also be placed close to the LTC3417 in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop "zero" at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective. Also, ceramic capacitors are prone to temperature effects which require the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must fulfill a charge storage requirement. During a load step, the output capacitor must
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instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear droop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately:
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COUT 2.5
IOUT fO * VDROOP
More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10F ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3417 develops a 0.8V reference voltage between the feedback pins, VFB1 and VFB2, and the signal ground as shown in Figure 4. The output voltages are set by two resistive dividers according to the following formulas:
R1 VOUT1 0.8 V 1 + R2 R3 VOUT2 0.8 V 1 + R4
Keeping the current small (<5A) in these resistors maximizes efficiency, but making the current too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor, CF, may also be used. Great care should be taken to route the VFB node away from noise sources, such as the inductor or the SW line.
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VRUN 2V/DIV VOUT 1V/DIV
IL 1A/DIV
VIN = 3.6V VOUT = 1.8V RL = 0.9
200s/DIV
Figure 2. Digital Soft-Start Out1
Soft-Start Soft-start reduces surge currents from VIN by gradually increasing the peak inductor current. Power supply sequencing can also be accomplished by controlling the ITH pin. The LTC3417 has an internal digital soft-start for each regulator output, which steps up a clamp on ITH over 1024 clock cycles, as can be seen in Figures 2 and 3. As the voltage on ITH ramps through its operating range, the internal peak current limit is also ramped at a proportional linear rate. Mode Selection The MODE pin provides mode selection. Connecting this pin to VIN enables Burst Mode operation for both regulators, which provides the best low current efficiency at the cost of a higher output voltage ripple. When MODE is connected to ground, pulse skipping operation is selected for both regulators, which provides the lowest output voltage and current ripple at the cost of low current efficiency. Applying a voltage that is more than 1V from either supply results in forced continuous mode for both regulators, which creates a fixed output ripple and allows the sinking of some current (about 1/2IL). Since the switching noise is constant in this mode, it is also the easiest to filter out. In many cases, the output voltage can be simply connected to the MODE pin, selecting the forced continuous mode except at start-up. Checking Transient Response The ITH pin compensation allows the transient response to be optimized for a wide range of loads and output capaci-
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tors. The availability of the ITH pin not only allows optimization of the control loop behavior, but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated using the percentage of overshoot seen at this pin or by examining the rise time at this pin. The ITH external components shown in the Figure 4 circuit will provide an adequate starting point for most applications. The series RC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because of various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD * ESRCOUT, where ESRCOUT is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time,
VRUN 2V/DIV VOUT 1V/DIV IL 0.5A/DIV VIN = 3.6V VOUT = 2.5V RL = 2 200s/DIV
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Figure 3. Digital Soft-Start Out2
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VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with RITH and the bandwidth of the loop increases with decreasing CITH. If RITH is increased by the same factor that CITH is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, feedforward capacitors, C1 and C2, can be added to improve the high frequency response, as shown in Figure 4. Capacitor C1 provides phase lead by creating a high frequency zero with R1 which improves the phase margin for the 1.4A SW1 channel. Capacitor C2 provides phase lead by creating a high frequency zero with R3 which improves the phase margin for the 800mA SW2 channel. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. Although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage VIN drops toward VOUT, the load step capability does decrease due to the decreasing voltage across the inductor. Applications that require large load step capability near dropout should use a different topology such as SEPIC, Zeta, or single inductor, positive buck boost. In some applications, a more severe transient can be caused by switching in loads with large (>1F) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this prob-
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lem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot SwapTM controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and softstarting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% - (P1+ P2 + P3 +...) where P1, P2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3417 circuits: 1) LTC3417 IS current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The IS current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. IS current results in a small (< 0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge moves from VIN to ground. The resulting charge over the switching period is a current out of VIN that is typically much larger than the DC bias current. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages.
Hot Swap is a trademark of Linear Technology Corporation.
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LTC3417
APPLICATIO S I FOR ATIO
3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and the external inductor, RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) where RL is the resistance of the inductor. 4) Other "hidden" losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESRCOUT at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations The LTC3417 requires the package Exposed Pad (PGND2/ GNDD pin) to be well soldered to the PC board. This gives the DFN and TSSOP packages exceptional thermal properties, compared to similar packages of this size, making it difficult in normal operation to exceed the maximum junction temperature of the part. In a majority of applications, the LTC3417 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3417 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both switches in both regulators will be turned off and the SW nodes will become high impedance.
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To prevent the LTC3417 from exceeding its maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD * JA where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3417 is in dropout in both regulators at an input voltage of 3.3V with load currents of 1.4A and 800mA. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the 1.4A P-channel switch is 0.09 and the RDS(ON) of the 800mA P-channel switch is 0.163. The power dissipated by the part is: PD = I12 * RDS(ON)1 + I22 * RDS(ON)2 PD = 1.42 * 0.09 + 0.82 * 0.163 PD = 281mW The DFN package junction-to-ambient thermal resistance, JA, is about 43C/W. Therefore, the junction temperature of the regulator operating in a 70C ambient temperature is approximately: TJ = 0.281 * 43 + 70 TJ = 82.1C Remembering that the above junction temperature is obtained from an RDS(ON) at 25C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125C.
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LTC3417
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Design Example
As a design example, consider using the LTC3417 in a portable application with a Li-Ion battery. The battery provides a VIN from 2.5V to 4.2V. One output requires 1.8V at 1.3A in active mode, and 1mA in standby mode. The other output requires 2.5V at 700mA in active mode, and 500A in standby mode. Since both loads still need power in standby, Burst Mode operation is selected for good low load efficiency (MODE = VIN). First, determine what frequency should be used. Higher frequency results in a lower inductor value for a given IL (IL is estimated as 0.35ILOAD(MAX)). Reasonable values for wire wound surface mount inductors are usually in the range of 1H to 10H.
CONVERTER OUTPUT SW1 SW2 ILOAD(MAX) 1.4A 800mA IL 490mA 280mA
Using the 1.5MHz frequency setting (FREQ = VIN), we get the following equations for L1 and L2: L1 = 1 . 8V 1 . 8V 1- = 1 . 4 H 1 . 5MHz * 490mA 4 . 2V
Use 1 . 5 H. L2 = 2 . 5V 2 . 5V 1- = 2 . 4 H 1 . 5MHz * 280mA 4 . 2V
Use 2 . 2 H.
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COUT selection is based on load step droop instead of ESR requirements. For a 5% output droop:
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COUT1 = 2 . 5 * COUT 2 = 2 . 5 *
1 . 3A = 24 F 1 . 5MHz ( 5 % * 1 . 8V ) 0 . 7A = 9 . 3 F 1 . 5MHz ( 5 % * 2 . 5V )
The closest standard values are 22F and 10F. The output voltages can now be programmed by choosing the values of R1, R2, R3, and R4. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2A with the 0.8V feedback voltages makes R2 and R4 equal to 400k. A close standard 1% resistor is 412k. This then makes R1 = 515k. A close standard 1% is 511k. Similarily, with R4 at 412k, R3 is equal to 875k. A close 1% resistor is 866k. The compensation should be optimized for these components by examining the load step response, but a good place to start for the LTC3417 is with a 5.9k and 2200pF filter on ITH1 and 2.87k and 6800pF on ITH2. The output capacitor may need to be increased depending on the actual undershoot during a load step. The PGOOD pin is a common drain output and requires a pull-up resistor. A 100k resistor is used for adequate speed. Figure 4 shows a complete schematic for this design.
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VIN 2.25V TO 5.5V
CIN 10F
VOUT1 1.8V 1.4A
L1 1.5H
C1 22pF
VIN
R1 511k
COUT1 22F
R2 412k R5 5.9k C3 2200pF
L1: MIDCOM DUS-5121-1R5R COUT1: KEMET C1210C226K8PAC
OUT1 Efficiency vs Load Current
100 VIN = 3.6V VOUT = 1.8V 95 FREQ = 1MHz REFER TO FIGURE 4 90 85 80 75 70 0.001 0.001 10
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EFFICIENCY (%)
Figure 4. 1.8V at 1.4A/2.5V at 800mA Step-Down Regulators
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CIN1 0.1F CIN2 0.1F
R7 100k
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VIN1 VIN2 MODE SW1 RUN1 LTC3417 VFB1 PHASE ITH1 VFB2 FREQ
VIN
R6 2.87k C4 6800pF
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PGOOD SW2 RUN2
VIN
L2 2.2H
C2 22pF
VOUT2 2.5V 800mA
R3 866k
R4 412k COUT2 10F
ITH2 EXPOSED GNDA PAD GNDD
L2: MIDCOM DUS-5121-2R2R COUT2, CIN: KEMET C1206C106K4PAC
10
1
POWER LOSS (W)
EFFICIENCY 0.1 POWER LOSS 0.01
0.01 0.1 1 LOAD CURRENT (A)
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Board Layout Considerations
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3417. These items are also illustrated graphically in the layout diagram of Figure 5. Check the following in your layout. 1. Does the capacitor CIN connect to the power VIN1 (Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as close as possible (DFN package)? It may be necessary to split CIN into two capacitors. This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT1, L1 and COUT2, L2 closely connected? The (-) plate of COUT1 returns current to PGND1, and the (-) plate of COUT2 returns current to the PGND2/GNDD and the (-) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT1 and a ground line terminated near GNDA. The resistor divider, R3 and R4,
VIN CIN 10F CIN2 0.1F VIN2 PGND2/ EXPOSED PAD GNDA L2 VOUT2 CC2 R3 VFB2 R4 STAR TO GNDA CITH2 VIN RITH2 R8 PGOOD RUN2 PHASE GNDD SW2
COUT2
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must be connected between the (+) plate of COUT2 and a ground line terminated near GNDA. The feedback signals VFB1 and VFB2 should be routed away from noise components and traces, such as the SW lines, and its trace should be minimized. 4. Keep sensitive components away from the SW pins. The input capacitor CIN, the compensation capacitors CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3, R4, RITH1 and RITH2 should be routed away from the SW traces and the inductors L1 and L2. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GNDA pin at one point which is then connected to the PGND2/GNDD pin. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to one of the input supplies.
VIN1 PGND1 COUT1 L1 SW1 CC1 R1 VFB1 R2 RITH1 R7 FREQ RUN1 MODE VIN CITH1 STAR TO GNDA VOUT1 CIN1 0.1F LTC3417 ITH2 ITH1
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Figure 5
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PACKAGE DESCRIPTIO
3.50 0.05
1.65 0.05 2.20 0.05 (2 SIDES)
0.25 0.05 0.50 BSC 4.40 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
6.60 0.10 4.50 0.10
SEE NOTE 4
RECOMMENDED SOLDER PAD LAYOUT
4.30 - 4.50* (.169 - .177)
0.09 - 0.20 (.0035 - .0079)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DHC Package 16-Lead Plastic DFN (5mm x 3mm)
(Reference LTC DWG # 05-08-1706)
R = 0.115 TYP R = 0.20 TYP 3.00 0.10 (2 SIDES) 1.65 0.10 (2 SIDES) PIN 1 NOTCH
(DHC16) DFN 1103
5.00 0.10 (2 SIDES) 0.65 0.05
0.40 0.10 16
9
PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF
8 0.75 0.05 4.40 0.10 (2 SIDES)
1 0.25 0.05 0.50 BSC
0.00 - 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
BOTTOM VIEW--EXPOSED PAD
FE Package 20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
4.95 (.195) 6.40 - 6.60* (.252 - .260) 4.95 (.195) 20 1918 17 16 15 14 13 12 11
2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10
6.40 2.74 (.252) (.108) BSC
0.25 REF
1.20 (.047) MAX
0 - 8
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE20 (CA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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RELATED PARTS
PART NUMBER LTC3404 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3407-2 LTC3409 LTC3411 LTC3412 LTC3413 LTC3414 LTC3416 LTC3418 LTC3440 LTC3441 LTC3443 LTC3448 LTC3548 DESCRIPTION 600mA (IOUT), 1.4MHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters COMMENTS 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10A, ISD < 1A, MS8 Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD < 1A, ThinSOTTM Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD < 1A, ThinSOT Package
Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, Converter ISD < 1A, MSE/DFN Packages Dual 800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 600mA, Low VIN (1.6V to 5.5V), Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, MSE/DFN Packages 95% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65A, ISD < 1A, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, MS Package
2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, TSSOP16E Package 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter with Tracking 8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 1.2A (IOUT), 600kHz, Synchronous Buck-Boost DC/DC Converter 1.5MHz/2.25MHz, 600mA Synchronous Step-Down DC/DC Converter with LDO Mode Dual 800mA and 400mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF/2, IQ = 280A, ISD < 1A, TSSOP16E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD < 1A, TSSOP20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD < 1A, TSSOP20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 380A, ISD < 1A, QFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.4V, IQ = 25A, ISD < 1A, MS/DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.4V, IQ = 25A, ISD < 1A, DFN Package 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN) = 2.4V, IQ = 28A, ISD < 1A, MS Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 32A, ISD < 1A, DFN/MS8E 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, MSE/DFN Packages
ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT/TP 0805 500 * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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Price & Availability of LTC3417

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